With the wide use of complex microprocessor-based systems in both consumer and industrial products, automation of testing and diagnosis of circuit faults, particularly of the kernel of such systems, has become extremely desireable. The kernel of such a system is well-understood in the art to refer to the microprocessor (.mu.P), itself, and the associated elements with which it is necessary for the microprocessor to correctly interact to function correctly, specifically the memory, clock, address bus and data bus. So-called emulative testers in which an element of the kernel is emulated by the testing apparatus have become popular for functional testing because they enable detailed diagnostics of the kernel even where the kernel is not even minimally operative.
One type of emulative tester is a microprocessor emulator, exemplified by the tester described in U.S. Pat. No. 4,455,654, issued to K. S. Bhaskar et al and assigned to the John Fluke Mfg. Co., Inc. In that system, connection is made to the UUT by removing the UUT .mu.P and connecting the test system through the .mu.P socket of the UUT.
Another type of emulative tester is a ROM (or memory) emulator. ROM emulation is deemed desireable since the ROM is in direct communication with the UUT data and address buses and the pin configurations of ROM sockets are relatively simple. ROM emulators are well known for use in software design and operational verification of the .mu.P but have only recently been used for fault detection and diagnosis because no sync signal is typically available to synchronize the test equipment with the test results it receives. A solution to this problem is disclosed in U.S. patent application Ser. No. 07/158,223, of M. H. Scott et al, filed Feb. 19, 1988, now U.S. Pat. No. 4,868,822 issued 9-19-89, for MEMORY EMULATION METHOD AND SYSTEM FOR TESTING AND TROUBLESHOOTING MICROPROCESSOR-BASED ELECTRONIC SYSTEMS, and is hereby fully incorporated by reference herein. That test system comprises a .mu.P-based mainframe and an interface pod which also includes a .mu.P-based system which is connected to both the .mu.P and the memory socket of the UUT. The interface pod includes special logic circuitry connected to the UUT .mu.P to provide a fine resolution sync signal pulse during a bus cycle of interest in order to provide full troubleshooting fault isolation that is as effective as that provided by prior art .mu.P emulation since the high resolution sync pulse derived from the .mu.P can be used to isolate and evaluate signals monitored from the address and data buses at the memory socket with the same facility as they could be from .mu.P connections. Also, as disclosed in that application, ROM emulation may be generalized to memory emulation (e.g. the emulation of any memory or portion of memory) since the trend in .mu.P-based systems is to increase RAM while reducing ROM and possibly eliminating ROM altogether by substituting RAM. Therefore test systems must be adequately generalized to test systems not yet produced but, nonetheless, foreseeable in light of current trends in electronic microprocessor-based system architecture.
It will be important to understand the distinction between terms indicating different degrees of certainty of functionality provided by different testing procedures. The term "verification", as used herein indicates the ascertaining of at least a minimum level of functionality which is sufficient to allow a subsequent procedure to be conducted. The term "validation" indicates that if no fault is found, the entire structure validated may be considered fully functional. The term "test" is used to indicate a procedure where all existing faults will be found, but not necessarily isolated or identified. "Diagnosis", as used herein, indicates that all faults are found and identified.
As disclosed in the above noted copending application, KERNEL TESTING INTERFACE AND METHOD FOR AUTOMATING DIAGNOSTICS OF MICROPROCESSOR-BASED SYSTEMS, by Polstra et al, which is hereby fully incorporated by reference, a highly automated testing and diagnostics system and method has been provided utilizing memory emulation. A difficulty is encountered, however, in the testing of systems using modern microprocessors (.mu.P) which utilize instruction prefetch logic which allows them to fetch instructions from memory before such instructions are actually needed. This logic causes the .mu.P to overlap instruction fetching with the execution of already fetched instructions, permitting better bus utilization and higher program execution speeds.
While instruction prefetch logic yields improved performance in the .mu.P, it causes difficulty in the testing of .mu.P-based systems using such .mu.Ps since instruction and data fetches are interleaved in an unpredictable order. The precise sequence of memory accesses is determined during program execution and may be affected by numerous factors such as .mu.P execution speed, memory access time and non-CPU transactions such as RAM refresh cycles. Since memory emulation testing is primarily based on analysis of the response of the system to a given stimulus, it is usually necessary to be able to associate a response with the stimulus which provoked it. Clearly, then, instruction prefetch logic presents a major obstacle to testing and to the extension of the capabilities of test equipment to the testing of systems using .mu.Ps having such a feature.